// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// PROGRAM		"Quartus II 64-Bit"
// VERSION		"Version 15.0.0 Build 145 04/22/2015 SJ Full Version"
// CREATED		"Sun Nov 29 03:53:00 2020"

module reg_8d(
	clk,
	reset,
	d,
	q
);


input wire	clk;
input wire	reset;
input wire	[7:0] d;
output wire	[7:0] q;

wire	[7:0] q_ALTERA_SYNTHESIZED;





D_FF	b2v_inst(
	.clk(clk),
	.reset(reset),
	.d(d[0]),
	.q(q_ALTERA_SYNTHESIZED[0]));


D_FF	b2v_inst1(
	.clk(clk),
	.reset(reset),
	.d(d[1]),
	.q(q_ALTERA_SYNTHESIZED[1]));


D_FF	b2v_inst2(
	.clk(clk),
	.reset(reset),
	.d(d[2]),
	.q(q_ALTERA_SYNTHESIZED[2]));


D_FF	b2v_inst3(
	.clk(clk),
	.reset(reset),
	.d(d[3]),
	.q(q_ALTERA_SYNTHESIZED[3]));


D_FF	b2v_inst4(
	.clk(clk),
	.reset(reset),
	.d(d[4]),
	.q(q_ALTERA_SYNTHESIZED[4]));


D_FF	b2v_inst5(
	.clk(clk),
	.reset(reset),
	.d(d[5]),
	.q(q_ALTERA_SYNTHESIZED[5]));


D_FF	b2v_inst6(
	.clk(clk),
	.reset(reset),
	.d(d[6]),
	.q(q_ALTERA_SYNTHESIZED[6]));


D_FF	b2v_inst7(
	.clk(clk),
	.reset(reset),
	.d(d[7]),
	.q(q_ALTERA_SYNTHESIZED[7]));

assign	q = q_ALTERA_SYNTHESIZED;

endmodule
